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SN8F5708 Datasheet(PDF) 151 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 151 Page - SONiX Technology Company |
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151 / 204 page ![]() www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. I2C Datasheet Rev. 2.4 151 22 I2C The I2C is a serial communication interface for data exchanging from one MCU to one MCU or other hardware peripherals. The device can transmit data as a master or a slave with two bi-directional IO, SDA (Serial data output) and SCL (Serial clock input). When a master transmit data to a slave, it’s called “WRITE” operation; when a slave transmit data to a master, it’s called “READ” operation. It also supports multi-master communication and keeps data transmission correctly by an arbitration method to decide one master has the control on bus and transmit its data. Master Tx, Rx Mode Slave Tx, Rx mode (with general address call) for multiplex slave in single master situation. 2-wire synchronous data transfer/receiver. Support 100K/400K clock rate. 22.1 I2C Protocol I2C transmission structure includes a START(S) condition, 8-bit address byte, one or more data byte and a STOP (P) condition. START condition is generated by master to initial any transmission. Data is transmitted with the Most Significant Bit (MSB) first. In address byte, the higher 7-bit is address bit and the lowest bit is data direction (R/W) bit. When R/W=0, it assigns a “WRITR” operation. When R/W=1, it assigns a “READ” operation. After each byte is received, the receiver (a master or a slave) must send an acknowledge (ACK). If transmitter can’t receive an ACK, it will recognize a not acknowledge (NACK). In WRITE operation, the master will transmit data to the slave and then waits for ACK from slave. In READ operation, the slave will transmit data to the master and then waits for ACK from master. In the end, the master will generate a STOP condition to finish transmission. S Transmit Address ACK 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 1 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 P SDA SCL Transmission Data R/W D7 Ack signal from receiver SCL held low, while interrupt executing NACK Nack signal from receiver START Condition STOP Condition |
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