SN8F5708 datasheet(155/204 Pages) SONIX

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SN8F5708 Series

I2C

Datasheet Rev. 2.4

155



Note:

1. The first step of I2C operation is to setup the I2C pins’ mode. Must be set “input

mode” in SDA/SCL pins.

2. When clock generator source is T1 overflow rate, the max counter value is 0xFB.

(Only supports 0x00~0xFB). And in this time if T1 clock rate is IHRC_32MHz, SCL

maximum clock rate is 800kHz.

3. If user wants to generate SCL clock rate is 100kHz/400kHz, you can set T1

counter value is 0xD8/0xF6 easily.

22.5

Synchronization and Arbitration

In multi-master condition, more than one master may transmit on bus in the same time. It must be

decided which master has the control of bus and complete its transmission. Clock synchronization

and arbitration are used to configure multi-master transmission. Clock synchronization is executed

by synchronizing the SCL signal with anther devices.

When two masters want to transmit data in the same, the clock synchronization will start by the

High to Low transition on the SCL. If master 1 clock set LOW first, it holds the SCL in LOW status

until the clock transit to HIGH status. However, if anther master clock still keep LOW status, the

Low to High transition of master 1 may not change SCL status (SCL keep LOW). In the other word,

SCL keep LOW by the master with the longest clock time in LOW status. The SCL will transit from

LOW to HIGH when the all devices clock transit to HIGH status. In the duration, the master1 will

keep in HIGH status and wait for SCL transition (from LOW to HIGH), then continue its transmission.

After clock synchronization, all devices clock and SCL clock are the same. Arbitration is used to

decide which master can complete its transmission by SDA signal. Two masters may send out a

START condition and transmit data on bus in the same time. They may influence by each other.

Arbitration will force one master to lose the control on bus. Data transmission will keep until

master output different data signal. If one master transmits HIGH status and anther master

transmits LOW status, the SDA will be pull low. The master output High will detect the different

with SDA and lose the control on bus. The mater with LOW status wins the bus control and

continues its transmission. There is no data miss during arbitration.

SN8F5708 Datasheet(PDF) 155 Page - SONiX Technology Company