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SN8F5708 Datasheet(PDF) 152 Page - SONiX Technology Company

Part # SN8F5708
Description  8051-based Microcontroller
PDF  204 Pages
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Manufacturer  SONIX [SONiX Technology Company]
Direct Link  http://www.sonix.com.tw
Logo SONIX - SONiX Technology Company

SN8F5708 Datasheet(HTML) 152 Page - SONiX Technology Company

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SN8F5708 Series
Copyright © 2019, SONiX Technology Co., Ltd.
I2C
Datasheet Rev. 2.4
152
22.2
I2C Transfer Modes
The I2C can operate as a master/slave to execute the 8-bit serial data transmission/reception
operation. Thus, the module can operate in one of four modes: Master Transmitter, Master
Receiver, Slave Transmitter and Slave Receiver.
22.2.1 Master Transmitter Mode
The master transmits information to the slave. The serial data is output via SDA while the serial
clock is output on SCL. Data transmission starts via generate a START(S) signal. After the START
signal, the specific address byte of slave device is sent. The address byte includes 7-bit address bit
and an 8th data direction (R/W) bit. The R/W is set “0” to enable the master transmission. In the
following, the master transmits one or more data byte to the slaver. After each data is transmitted,
the master waits for the acknowledge (ACK) from the slave. In the end, the master generates a
STOP (P) signal to terminate the data transmission.
S
Slave Address
W
A
DATA
A
A/N P
...
DATA
Transmit signal
Receive signal
S = Start status
P = Stop status
A = ACK
N = NACK
W = Write operation
R = Read operation
Interrupt
Interrupt
Interrupt
Interrupt
22.2.2 Master Receiver Mode
The master receives the information from the slave. The serial data input via SDA while the serial
clock output on SCL. Data reception starts via generate a START(S) signal. After the START signal,
the specific address byte of slave device is sent. The address byte includes 7-bit address bit and an
8th data direction (R/W) bit. The R/W is set “1” to enable the master reception. In the following,
the master receives one or more data byte from the slaver. After each data is received, the master
generates the acknowledge (ACK) or not acknowledge (NACK) to the slave via the status of AA bit.
In the end, the master generates a STOP (P) signal to terminate the data transmission.
S
Slave Address
R
A
DATA
A
A/N P
...
DATA
Transmit signal
Receive signal
S = Start status
P = Stop status
A = ACK
N = NACK
W = Write operation
R = Read operation
Interrupt
Interrupt
Interrupt
Interrupt



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