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SN8F5708 Datasheet(PDF) 148 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 148 Page - SONiX Technology Company |
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148 / 204 page ![]() www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. SPI Datasheet Rev. 2.4 148 SPSTA Register (0xE1) Bit Field Type Initial Description 7 SPIF R 0 SPI complete communication flag Set automatically at the end of communication Cleared automatically by reading SPSTA, SPDAT registers 6 WCOL R 0 Write collision flag Set automatically if write SPDAT during communication Cleared automatically by reading SPSTA, SPDAT registers 5 SSERR R 0 Synchronous slave select pin error Set automatically if SSN error controlling Cleared automatically by clear SPEN 4 MODF R 0 Mode fault flag 3..0 Reserved R 0x00 SPDAT Register (0xE3) Bit Field Type Initial Description 7..0 SPDAT R/W 0x00 Master mode: action of writing data triggers SPI communication; reception data is readable after the end of one byte communication (SPIF automatically set). Slave mode: written data would be transmitted by SCK input; reception data is available to read after the end of one byte communication (SPIF automatically set). IEN0 Register (0xA8) Bit Field Type Initial Description 7 EAL R/W 0 Interrupts enable. Refer to Chapter Interrupt Else Refer to other chapter(s) IEN1 Register (0xB8) Bit Field Type Initial Description 1 ESPI R/W 0 Enable SPI interrupt Else Refer to other chapter(s) |
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