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SN8F5708 Datasheet(PDF) 144 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 144 Page - SONiX Technology Company |
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144 / 204 page  www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. SPI Datasheet Rev. 2.4 144 C P O L C P H A Diagrams Description 0 1 bit5 bit4 bit3 bit2 bit1 bit6 bit7 bit0 SCK idle status = Low. The transfer first bit = MSB. SCK data transfer edge = Falling edge. 1 1 bit5 bit4 bit3 bit2 bit1 bit6 bit7 bit0 SCK idle status = High. The transfer first bit = MSB. SCK data transfer edge = Rising edge. 0 0 bit5 bit4 bit3 bit2 bit1 bit6 bit7 bit0 Next data SCK idle status = Low. The transfer first bit = MSB. SCK data transfer edge = Rising edge. 1 0 bit5 bit4 bit3 bit2 bit1 bit6 bit7 bit0 Next data SCK idle status = High. The transfer first bit = MSB. SCK data transfer edge = Falling edge. The SPI supports interrupt function. ESPI is SPI interrupt function control bit. ESPI=0, disable SPI interrupt function. ESPI=1, enable SPI interrupt function. When SPI interrupt function enable, the program counter points to interrupt vector to do SPI interrupt service routine after SPI operating. SPIF is SPI interrupt request flag, and also to be the SPI operating status indicator when ESPI= 0, but cleared by reading the SPSTA, SPDAT registers. SPI builds in chip selection function to implement SPI multi-device mode. One master communicating with several slave devices in SPI bus, and the chip selection decides the pointed device. The chip selection pin is SSN pin. The SPI pins also support open-drain structure. The open-drain option is controlled by PnOC bits. When PnOC=0, disable SPI open-drain structure. When PnOC=1, enable SPI open-drain structure. If enable open-drain structure, SPI pins must be set input mode and need external pull-up resistor. |
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