SN8F5708 datasheet(145/204 Pages) SONIX

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SN8F5708 Series

SPI

Datasheet Rev. 2.4

145

21.2

SPI Master

The SPI master mode has seven types of clock generator from fcpu/2 to fcpu/128. Generated clock

is outputted through SCK pin (shared with P1.3) and its idle status is controlled by CPOL.

The phase of data input and output is automatically specified by CPHA register. In master mode

MOSI pin (shared with P1.1) plays the role of data output, and MISO pin (shared with P1.2) fetches

data from slave device. A SPI communication is started by writing SPDAT register; the received data

from MISO is available to read after the end of data transmission.

The master mode has two status flags with interrupt function:

SPIF register indicates the end of one byte data communication. An interrupt would be issued at

the same time if ESPI bit is enabled.

MODF is issued by SSN (shared with P0.7) low status while transmission. This interrupt source can

be masked by setting SSDIS bit.

21.3

SPI Slave

The SPI slave mode monitors SCK pin to control its MISO and MOSI communication. However, the

maximum clock rate is limited at fcpu/8. Slave device(s) are expected to specify its CPOL and CPHA

setting as the same configuration of the connected SPI bus.

The slave mode treats MOSI pin as its data input, and MISO pin as its data transmission. By default,

the SSDIS register is low which means the slave select pin (SSN) is functional. A SPI communication

would be processed if the SSN is low status. Thus, a slave device is suspended if its SSN is high

status. But in CPHA = 0, Strictly SSN must follow each 8-bit data needs to be included with falling

edge and rising edge, CPHA=1 is not limitation.

MOSI

MISO

MOSI

MISO

SSN

(CPHA=1)

SSN

(CPHA=0)

SCK

MOSI

MISO

SN8F5708 Datasheet(PDF) 145 Page - SONiX Technology Company