SN8F5708 datasheet(153/204 Pages) SONIX

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SN8F5708 Series

I2C

Datasheet Rev. 2.4

153

22.2.3 Slave Transmitter Mode

The slave transmits information to the master. The serial data output via SDA while the serial clock

input on SCL. Data transmission starts via receive a START(S) signal from the master. After the

START signal, the specific address byte of slave device is received. The address byte includes 7-bit

address bit and an 8th data direction (R/W) bit. The R/W is set “1” to enable the slave transmission.

If the received address byte match the address in I2CADR register, the slave generate an

acknowledge (ACK). Otherwise, if general call address condition is set (GC=1), the slave also

generate an acknowledge (ACK) after general call address (0x00) is received. In the following, the

slave transmits one or more data byte to the master. After each data is transmitted, the slave waits

for the acknowledge (ACK) from the master. In the end, the slave receives a STOP (P) signal from

the master to terminate the data transmission.

Slave Address

DATA

A/N P

...

DATA

Transmit signal

Receive signal

S = Start status

P = Stop status

A = ACK

N = NACK

W = Write operation

R = Read operation

Interrupt

22.2.4 Slave Receiver Mode

The slave receives information from the master. Both the serial data and the serial clock are input

on SDA and SCL. Data reception starts via receive a START(S) signal from the master. After the

START signal, the specific address byte of slave device is received. The address byte includes 7-bit

address bit and an 8th data direction (R/W) bit. The R/W is set “0” to enable the slave reception. If

the received address byte match the address in I2CADR register, the slave generate an

acknowledge (ACK). Otherwise, if general call address condition is set (GC=1), the slave also

generate an acknowledge (ACK) after general call address (0x00) is received. In the following, the

slave receives one or more data byte from the master. After each data is receives, the slave

generates the acknowledge (ACK) or not acknowledge (NACK) to the master via the status of AA bit.

In the end, the slave receives a STOP (P) signal from the master to terminate the data transmission.

Slave Address

DATA

A/N P

...

DATA

Transmit signal

Receive signal

S = Start status

P = Stop status

A = ACK

N = NACK

W = Write operation

R = Read operation

Interrupt

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