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SN8F5708 Datasheet(PDF) 157 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 157 Page - SONiX Technology Company |
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157 / 204 page  www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. I2C Datasheet Rev. 2.4 157 When the SMBus extension function is enabled the lower 3-bit of I2CSTA hold the information about time out as the table below. I2CSTA Description XXXX X000 No timeout errors. XXXX XXX1 Tout timeout error. XXXX XX1X Tsext timeout error. XXXX X1XX Tmext timeout error. 22.7 I2C Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CDAT I2CDAT7 I2CDAT6 I2CDAT5 I2CDAT4 I2CDAT3 I2CDAT2 I2CDAT1 I2CDAT0 I2CADR ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 GC I2CCON CR2 ENS1 STA STO SI AA CR1 CR0 I2CSTA I2CSTA7 I2CSTA6 I2CSTA5 I2CSTA4 I2CSTA3 I2CSTA2 I2CSTA1 I2CSTA0 SMBSEL SMBEXE - - - - SMBSTP2 SMBSTP1 SMBSTP0 SMBDST SMBD7 SMBD6 SMBD5 SMBD4 SMBD3 SMBD2 SMBD1 SMBD0 IEN0 EAL - ET2 ES0 ET1 EX1 ET0 EX0 IEN1 ET2RL - ET2C3 ET2C2 ET2C1 ET2C0 ESPI EI2C P1M P17M P16M P15M P14M P13M P12M P11M P10M P1 P17 P16 P15 P14 P13 P12 P11 P10 I2CDAT Register (0xDA) Bit Field Type Initial Description 7:0 I2CDAT[7:0] R/W 0x00 The I2CDAT register contains a byte to be transmitted through I2C bus or a byte which has just been received through I2C bus. The CPU can read from and write to this 8-bit, directly addressable SFR while it is not in the process of byte shifting. The I2CDAT register is not shadowed or double buffered so the user should only read I2CDAT when an I2C interrupt occurs. I2CADR Register (0xDB) Bit Field Type Initial Description 7:1 I2CADR[6:0] R/W 0x00 I2C slave address 0 GC R/W 0 General call address (0X00) acknowledgment 0: ignored 1: recognized |
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