SN8F5708 datasheet(158/204 Pages) SONIX

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SN8F5708 Series

I2C

Datasheet Rev. 2.4

158

I2CCON Register (0xDC)

Bit

Field

Type

Initial

Description

7,1,0 CR[2:0]

R/W

I2C clock rate

000: fcpu/256

001: fcpu/224

010: fcpu/192

011: fcpu/160

100: fcpu/960

101: fcpu/120

110: fcpu/60

111: Timer 1 overflow-period/8

ENS1

R/W

I2C functionality

0: Disable

1: Enable

STA

R/W

START flag

0: No START condition is transmitted.

1: A START condition is transmitted if the bus is free.

STO

R/W

STOP flag

0: No STOP condition is transmitted.

1: A STOP condition is transmitted to the I2C bus in

master mode.

R/W

Serial interrupt flag

The SI is set by hardware when one of 25 out of 26

possible I2C states is entered. The only state that does

not set the SI is state F8h, which indicates that no

relevant state information is available. The SI flag must

be cleared by software. In order to clear the SI bit, ‘0’

must be written to this bit. Writing a ‘1’ to SI bit does

not change value of the SI.

R/W

Assert acknowledge flag

0: A NACK will be returned when a byte has received

1: An ACK will be returned when a byte has received

I2CSTA Register (0xDD)

Bit

Field

Type

Initial

Description

7:3

I2CSTA[7:3]

11111

I2C Status Code

2..0

I2CSTA[2:0]

000

SMBus Status Code

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