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SN8F5708 Datasheet(PDF) 128 Page - SONiX Technology Company |
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SN8F5708 Datasheet(HTML) 128 Page - SONiX Technology Company |
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128 / 204 page  www.sonix.com.tw SN8F5708 Series Copyright © 2019, SONiX Technology Co., Ltd. ADC Datasheet Rev. 2.4 128 ADB Register (0xD3) Bit Field Type Initial Description 7..0 ADB[11:4] R - ADC Result Bit [11:4] * in 12-bit ADC resolution mode. * ADC data buffer is 12-bit length to store ADC converter result. The high byte is ADB register, and the low-nibble is ADR[3:0] bits. ADR Register (0xD4) Bit Field Type Initial Description 6 GCHS R/W 0 ADC global channel select bit. 0: Disable AIN channel. 1: Enable AIN channel. 5..4 ADCKS[1:0] R/W 00 ADC’s clock source select bit. 00 = fosc/16, 01 = fosc/8, 10 = fosc/1, 11 = fosc/2 3..0 ADB[3:0] R - ADC Result Bit [3:0] * in 12-bit ADC resolution mode. * ADC data buffer is 12-bit length to store ADC converter result. The high byte is ADB register, and the low-nibble is ADR[3:0] bits. |
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