SN8F5708 datasheet(136/204 Pages) SONIX

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SN8F5708 Series

UART

Datasheet Rev. 2.4

136

the stop bit.

Data reception is controlled by REN0 bit. When REN0=1, data reception function is enabled. Data

reception starts by receiving the start bit for master terminal, URX detects the falling edge of start

bit, and then the RI0 flag is set in the middle of a stop bit. Until reception completion, input data is

stored in S0BUF register and the stop bit is stored in RB80.

Start

Stop

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

20.4

Mode 2: 9-bit Receiver/Transmitter with Fixed Baud Rate

Mode2 supports an asynchronous 9-bit UART with fixed baud rate. The transfer format includes 1

start bit, 9 data bits (LSB first) and 1 stop bit. Data is transmitted by UTX pin and received by URX

pin. The baud rate clock source is fixed to fcpu/64 or fcpu/32 and is controlled by SMOD bit. When

SMOD=0, baud rate is fcpu/64. When SMOD=1, baud rate is fcpu/32.

Data transmission is controlled by REN0 bit. After transmission configuration, load transmitted

data into S0BUF, and then UART starts to transmit the pocket. The 9th data bit is taken from TB80.

The TI0 flag is set at the beginning of the stop bit.

Data reception is controlled by REN0 bit. When REN0=1, data reception function is enabled. Data

reception starts by receiving the start bit for master terminal, URX detects the falling edge of start

bit, and then the RI0 flag is set in the middle of a stop bit. Until reception completion, lower 8-bit

input data is stored in S0BUF register and the 9th bit is stored in RB80.

Start

Stop

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

bit8

20.5

Mode 3: 9-bit Receiver/Transmitter with Variable Baud Rate

Mode3 supports an asynchronous 9-bit UART with variable baud rate. The transfer format includes

1 start bit, 9 data bits (LSB first) and 1 stop bit. Data is transmitted by UTX pin and received by URX

pin. The different between Mode2 and Mode3 is baud rate selection. In the Mode3, the baud rate

clock source can be baud rate generator or T1 overflow controlled by BD bit. When BD=0, the baud

rate clock source is from T1 overflow. When BD=0, the baud rate clock source is from baud rate

generator controlled by S0RELH and S0RELL. Additionally, the baud rate can be doubled by SMOD

bit.

Data transmission is controlled by REN0 bit. After transmission configuration, load transmitted

SN8F5708 Datasheet(PDF) 136 Page - SONiX Technology Company

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