SN8F5708 datasheet(137/204 Pages) SONIX

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SN8F5708 Series

UART

Datasheet Rev. 2.4

137

data into S0BUF, and then UART starts to transmit the pocket. The 9th data bit is taken from TB80.

The TI0 flag is set at the beginning of the stop bit.

Data reception is controlled by REN0 bit. When REN0=1, data reception function is enabled. Data

reception starts by receiving the start bit for master terminal, URX0 detects the falling edge of start

bit, and then the RI0 flag is set in the middle of a stop bit. Until reception completion, lower 8-bit

input data is stored in S0BUF register and the 9th bit is stored in RB80.

Start

Stop

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

bit8

20.6

Multiprocessor Communication

UART supports multiprocessor communication between a master device and one or more slaver

device in Mode2 and Mode3 (9-bit UART). The master identifies correct slavers by using the 9th

data bit. When the communication starts, the master transmits a specific address byte with the 9th

bit is set “1” to selected slavers, and then transmits a data byte with the 9th bit is set “0” in the

following transmission.

Multiprocessor communication is controlled by SM20 bit. When SM20=0, disable multiprocessor

communication. When SM20=1, enable multiprocessor communication. If SM20 is set, the UART

reception interrupt is only generated when the 9th received bit is “1” (RB80). The slavers will

compare received data with its own address data by software. If address byte is match, the slavers

clear SM20 bit to enable interrupt function in the following data transmission. The slavers with

unmatched address, their SM20 keep in “1” and will not generate interrupt in the following data

transmission.

20.7

Baud Rate Control

The UART mode 0 has a fixed baud rate at fcpu/12, and the mode 2 has two baud rate selection

which is chosen by SMOD register: fcpu/64 (SMOD = 0) and fcpu/32 (SMOD = 1).

The baud rate of UART mode 1 and mode 3 is generated by either S0RELH/S0RELL registers (BD = 1)

or Timer 1 overflow period (BD = 0). The SMOD bit doubles the frequency from the generator.

If the S0RELH/S0RELL is selected (BD = 1) in mode 1 and 3, the baud rate is generated as following

equation.

Baud Rate = 2SMOD ×

fcpu

64 × (1024 − S0REL)

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