71M6541DSLASHFSLASHG datasheet(129/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

Rev 5

129

status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in

CESTATUS is shown in Table 81.

Table 81: CESTATUS (CE RAM 0x80) Bit Definitions

CESTATUS

bit

Name

Description

31:4

Not Used

These unused bits are always zero.

F0 is a square wave at the exact fundamental input frequency.

Not Used

This unused bit is always zero.

SAG_B

Normally zero. Becomes one when VB remains below SAG_THR for

SAG_CNT samples. Does not return to zero until VB rises above

SAG_THR.

SAG_A

Normally zero. Becomes one when VA remains below SAG_THR for

SAG_CNT samples. Does not return to zero until VA rises above

SAG_THR.

The CE is initialized by the MPU using CECONFIG (Table 82). This register contains in packed form

SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are

given in Table 83.

Table 82: CECONFIG Register

Address

Name

Data

Description

0x20

CECONFIG

0x0030DB00

0x00B0DB00

See description of the CECONFIG bits in

Table 83.

Default for CE41A01 (71M6541D/F/G or CE41A04 (71M6542F/G) CE code for use with local

sensors.

Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote

sensors.

Table 83: CECONFIG (CE RAM 0x20) Bit Definitions

CECONFIG

bit

Name

Default

Description

Reserved

Reserved (can be used by the MPU to indicate that the

71M6x01 is being used; CE does not use this).

EXT_TEMP

When 1, the MPU controls temperature compensation via the

GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, the CE is in

control.

EDGE_INT

When 1, XPULSE produces a pulse for each zero-crossing of

the mains phase selected by FREQSEL[1:0] , which can be used

to interrupt the MPU.

SAG_INT

When 1, activates YPULSE output when a sag condition is

detected.

19:8

SAG_CNT

252

(0xFC)

The number of consecutive voltage samples below SAG_THR

(CE RAM 0x24) before a sag alarm is declared. The default value

is equivalent to 100 ms.

7:6

FREQSEL[1:0]

FREQSEL[1:0] selects the phase to be used for the frequency

monitor, sag detection, and for the zero crossing counter

(MAINEDGE_X, CE RAM 0x83).

FREQ SEL[1:0]

Phase Selected

Not allowed

*71M6542F/G only

71M6541D/F/G Datasheet(PDF) 129 Page - Maxim Integrated Products

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