71M6541DSLASHFSLASHG datasheet(130/166 Pages) MAXIM

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71M6541D/F/G and 71M6542F/G Data Sheet

130

Rev 5

EXT_PULSE

When zero, causes the pulse generators to respond to internal

data (WPULSE = WSUM_X (CE RAM 0x84), VPULSE = VARSUM_X

(CE RAM 0x88)). Otherwise, the generators respond to values the

MPU places in APULSEW and APULSER (CE RAM 0x45 and 0x49).

4:2

Reserved

Reserved.

PULSE_FAST

When PULSE_FAST = 1, the pulse generator input is increased

16x. When PULSE_SLOW = 1, the pulse generator input is

reduced by a factor of 64. These two parameters control the

pulse gain factor X (see table below). Allowed values are either

1 or 0. Default is 0 for both (X = 6).

PULSE_FAST PULSE_SLOW

1.5 * 2

2 = 6

1.5 * 2

6 = 96

1.5 * 2

-4 = 0.09375

Do not use

PULSE_SLOW

The FREQSEL[1:0] field in CECONFIG (CE RAM 0x20[7:6]) selects the phase that is utilized to generate a sag

interrupt. Thus, a SAG_INT event occurs when the selected phase has satisfied the sag event criteria as

set by the SAG_THR (CE RAM 0x24) register and the SAG_CNT field in CECONFIG (CE RAM 0x20[19:8]).

When the SAG_INT bit (CE RAM 0x20[20]) is set to 1, a sag event generates a transition on the YPULSE

output. In a two-phase system (71M6542F/G), and after a sag interrupt, the MPU should change the

FREQSEL[1:0] setting to select the other phase, if it is powered. Even though a sag interrupt is only

generated on the selected phase, both phases are simultaneously checked for sag. The presence of

power on a given phase can be sensed by directly checking the SAG_A and SAG_B bits in CESTATUS (CE

RAM 0x80[0:1]).

The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)

temperature compensation is enabled.

The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by

the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external

pulse generation) by placing values into APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting

EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE

RAM 0x88).

The 71M6541D/F/G and 71M6542F/G Demo Code creep function halts both internal and external

pulse generation.

Table 84: Sag Threshold and Gain Adjust Control

Address

Name

Default

Description

0x24

SAG_THR

2.39*10

The voltage threshold for sag warnings. The default value is

equivalent to 113Vpk or 80 Vrms if VMAX = 600 Vrms.

��_��= ��∙√2

��∙7.8798∙10−9

0x40

GAIN_ADJ0

16384

This register scales the voltage measurement channels VA and

VB*. The default value of 16384 is equivalent to unity gain (1.000).

*71M6542F/G only

0x41

GAIN_ADJ1

16384

This register scales the IA current channel for Phase A. The

default value of 16384 is equivalent to unity gain (1.000).

0x42

GAIN_ADJ2

16384

This register scales the IB current channel for Phase B. The

default value of 16384 is equivalent to unity gain (1.000).

71M6541D/F/G Datasheet(PDF) 130 Page - Maxim Integrated Products

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