BQ25713 datasheet(18/111 Pages) TI2

18 / 111 page

7.5 Electrical Characteristics(BQ25730) (continued)

VVBUS_UVLOZ < VVBUS < VVBUSOV_FALL , TJ = -40°C to +125°C, and TJ = 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

RDS_LO_ON_Q2

The resistance of the

gate driver loop for

turning on Q2

VBTST1 - VSW1 = 5.5 V

RDS_LO_OFF_Q2

The resistance of the

gate driver loop for

turning off Q2

VBTST1 - VSW1 = 5.5 V

1.7

2.6

PWM LOW SIDE DRIVER (LODRV Q3)

RDS_LO_ON_Q3

The resistance of the

gate driver loop for

turning on Q3

VBTST2 - VSW2 = 5.5 V

6.8

RDS_LO_OFF_Q3

The resistance of the

gate driver loop for

turning off Q3

VBTST2 - VSW2 = 5.5 V

2.2

4.6

INTERNAL SOFT START During Charge Enable

SSSTEP_SIZE

Charge current soft-

start step size

SSSTEP_TIME

Charge current soft-

start duration time for

each step

INTEGRATED BTST DIODE (D1)

VF_D1

Forward bias voltage IF = 20 mA at 25°C

0.8

VR_D1

Reverse breakdown

voltage

IR = 2 µA at 25°C

INTEGRATED BTST DIODE (D2)

VF_D2

Forward bias voltage IF = 20 mA at 25°C

0.8

VR_D2

Reverse breakdown

voltage

IR = 2 µA at 25°C

INTERFACE

LOGIC INPUT (SDA, SCL)

VIN_ LO

Input low threshold

I2C

0.4

VIN_ HI

Input high threshold

I2C

1.3

LOGIC OUTPUT OPEN DRAIN (SDA, CHRG_OK, CMPOUT)

VOUT_ LO

Output saturation

voltage

5 mA drain current

0.4

VOUT_ LEAK

Leakage current

Voltage = 7 V

–1

µA

LOGIC INPUT (OTG/VAP/FRS pin)

VIN_ LO_OTG

Input low threshold

0.4

VIN_ HI_OTG

Input high threshold

1.3

LOGIC OUTPUT OPEN DRAIN SDA

VOUT_ LO_SDA

Output Saturation

Voltage

5 mA drain current

0.4

VOUT_ LEAK_SDA

Leakage Current

Voltage = 7 V

–1

µA

LOGIC OUTPUT OPEN DRAIN CHRG_OK

VOUT_ LO_CHRG_OK

Output Saturation

Voltage

5 mA drain current

0.4

VOUT_ LEAK _CHRG_OK Leakage Current

Voltage = 7 V

–1

µA

LOGIC OUTPUT OPEN DRAIN CMPOUT

VOUT_ LO_CMPOUT

Output Saturation

Voltage

5 mA drain current

0.4

BQ25730

SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024

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