BQ25713 datasheet(27/111 Pages) TI2

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8.3 Feature Description

8.3.1 Power-Up Sequence

The device powers up from the higher voltage of VBUS or VBAT through integrated power selector. The charger

starts POR (power on reset) when VBUS exceeds VVBUS_UVLOZ or VBAT exceeds VVBAT_UVLOZ. 5 ms after either

VBUS or VBAT becomes valid, the charger resets all the registers to the default state. Another 5 ms later, the

user registers become accessible to the host.

Power up sequence when the charger is powered up from VBUS:

• After VBUS above VVBUS_UVLOZ, enable 6-V LDO REGN pin and VDDA pin voltage increase accordingly.

CHRG_OK pin goes HIGH and the AC_STAT is configured to 1.

• After passing VBUS qualification, the REGN voltage is setup. VINDPM is detected in VBUS steady state

voltage and IIN_DPM is detected at ILIM_HIZ pin steady state voltage.

• Battery CELL configuration is read at CELL_BATPRESZ pin voltage and compared to VDDA to determine

cell configuration. Corresponding the default value of ChargeVoltage register (REG0x05/04()), ChargeCurrent

• Converter powers up.

Power up sequence when the charger is powered up from VBAT:

• If only battery is present and the voltage is above VVBAT_UVLOZ , charger wakes up and the BATFET is turned

on and connecting the battery to system.

• By default, the charger is in low power mode (EN_LWPWR = 1b) with lowest quiescent current. The

REGN LDO stays off. The Quiescent current is minimized. PROCHOT is available through the independent

comparator by setting EN_PROCHOT_LPWR=1b.

• The adapter present comparator is activated, to monitor the VBUS voltage.

• SDA and SDL lines stand by waiting for host commands.

• Device can move to performance mode by configuring EN_LWPWR = 0b. The host can enable IBAT

buffer through setting EN_IBAT=1b to monitor discharge current. The PSYS, PROCHOT or the independent

comparator also can be enabled by the host.

• In performance mode, the REGN LDO is always available to provide an accurate reference and gate drive

voltage for the converter.

8.3.2 Two-Level Battery Discharge Current Limit

To prevent the triggering of battery overcurrent protection and avoid battery wear-out, two battery current

limit levels (IDCHG_TH1 and IDCHG_TH2) PROCHOT profiles are recommended to be enabled. Define

IDCHG_TH1 through REG0x39h[7:2], IDCHG_TH2 is set through REG0x3Ch[5:3] for fixed percentage of

IDCHG_TH1. There are dedicated de-glitch time setting registers(IDCHG_DEG1 and IDCHG_DEG2) for both

IDCHG_TH1 and IDCHG_TH2.

• When battery discharge current is continuously higher than IDCHG_TH1 for more than IDCHG_DEG1 de-

glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH1,

then the time counter resets automatically. STAT_IDCHG1 bit will be set to 1 after PROCHOT is triggered.

Set PP_IDCHG1=1b to enable IDCHG_TH1 for triggering PROCHOT.

• When battery discharge current is continuously higher than IDCHG_TH2 for more than IDCHG_DEG2 de-

glitch time, PROCHOT is asserted immediately. If the discharge current reduces to lower than IDCHG_TH2,

then the time counter resets automatically. STAT_IDCHG2 bit will be set to 1 after PROCHOT is triggered.

Set PP_IDCHG2=1b to enable IDCHG_TH2 for triggering PROCHOT.

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BQ25730

SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024

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