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BQ25713 Datasheet(PDF) 41 Page - Texas Instruments

Part # BQ25713
Description  BQ25730 I2C 1- to 5-Cell Buck-Boost Narrow VDC Battery Charge Controller with Power Path Control and USB-C PD 3.0 OTG Output
PDF  111 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

BQ25713 Datasheet(HTML) 41 Page - Texas Instruments

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START (S)
STOP (P)
SDA
SCL
SDA
SCL
Figure 8-9. START and STOP Conditions
8.5.1.4 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the host into a wait state (clock stretching). Data
transfer then continues when the target is ready for another byte of data and release the clock line SCL.
SCL
SDA
START or
Repeated
START
S or Sr
1
2
7
8
9
MSB
ACK
Acknowledgement
signal from slave
1
2
8
9
ACK
Acknowledgement
signal from receiver
STOP or
Repeated
START
P or Sr
Figure 8-10. Data Transfer on the I2C Bus
8.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9th clock pulse, are generated by the host.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The host can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
8.5.1.6 Target Address and Data Direction Bit
After the START, a target address is sent. This address is 7 bits long followed by the eighth bit as a data
direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SCL
SDA
START
S
1-7
8
9
ACK
1-7
8
9
ACK
1-7
8
9
STOP
P
ADDRESS
R/W
DATA
ACK
DATA
Figure 8-11. Complete Data Transfer
www.ti.com
BQ25730
SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024
Copyright © 2024 Texas Instruments Incorporated
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