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BQ25713 Datasheet(PDF) 46 Page - Texas Instruments |
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BQ25713 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 111 page  8.6.1 ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh] Figure 8-16. ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh] 7 6 5 4 3 2 1 0 EN_LWPWR WDTMR_ADJ IIN_DPM_AUT O_DISABLE OTG_ON_CH RGOK EN_OOA PWM_FREQ LOW_PTM_RIP PLE R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN_CMP_LAT CH VSYS_UVP_E NZ EN_LEARN IADPT_GAIN IBAT_GAIN EN_LDO EN_IIN_DPM CHRG_INHIBIT R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-8. ChargeOption0 Register (I2C address = 01h) Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7 EN_LWPWR R/W 1b Low Power Mode Enable, under low power mode lowest quiescent current is achieved when only battery exist. It is not recommended to enable low power mode when adapter present. 0b: Disable Low Power Mode. Device in performance mode with battery only. The PROCHOT, current/power monitor buffer and comparator follow register setting. 1b: Enable Low Power Mode. Device in low power mode with battery only for lowest quiescent current. The REGN is off. The PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled. ADC is not available in Low Power Mode. Independent comparator and its low power mode PROCHOT profile can be enabled by setting EN_PROCHOT_LPWR bit to 1b. <default at POR> 6-5 WDTMR_ADJ R/W 11b WATCHDOG Timer Adjust Set maximum delay between consecutive Host write of charge voltage or charge current command. If device does not receive a write on the REG0x04() or the REG0x02() within the watchdog time period, the charger will be suspended by setting the REG0x02() to 0 mA. After expiration, the timer will resume upon the write of REG0x02(), REG0x04() or REG0x00[14:13]. 00b: Disable Watchdog Timer 01b: Enabled, 5 sec 10b: Enabled, 88 sec 11b: Enable Watchdog Timer, 175 sec <default at POR> 4 IIN_DPM_AUTO_DISAB LE R/W 0b IIN_DPM Auto Disable When CELL_BATPRESZ pin is LOW, the charger automatically disables the IIN_DPM function by setting EN_IIN_DPM (REG0x00[1]) to 0. The host can enable IIN_DPM function later by writing EN_IIN_DPM bit (REG0x00[1]) to 1. 0b: Disable this function. IIN_DPM is not disabled when CELL_BATPRESZ goes LOW. <default at POR> 1b: Enable this function. IIN_DPM is disabled when CELL_BATPRESZ goes LOW. 3 OTG_ON_CHRGOK R/W 0b Add OTG to CHRG_OK Drive CHRG_OK to HIGH when the device is in OTG mode. 0b: Disable <default at POR> 1b: Enable BQ25730 SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024 www.ti.com 46 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: BQ25730 |
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