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BQ25713 Datasheet(PDF) 73 Page - Texas Instruments |
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BQ25713 Datasheet(HTML) 73 Page - Texas Instruments |
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73 / 111 page  8.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h] Figure 8-31. ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h] 7 6 5 4 3 2 1 0 ADC_CONV ADC_START ADC_FULLSCA LE Reserved R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN_ADC_CMPI N EN_ADC_VBU S EN_ADC_PSY S EN_ADC_IIN EN_ADC_IDCH G EN_ADC_ICHG EN_ADC_VSY S EN_ADC_VBAT R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset The ADC registers are read in the following order: VBAT, VSYS, ICHG, IDCHG, IIN, PSYS, VBUS, CMPIN. ADC is disabled in low power mode. Before enabling ADC, low power mode should be disabled first. Table 8-38. ADCOption Register (I2C address = 3Bh) Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7 ADC_CONV R/W 0b Typical each ADC channel conversion time is 25 ms maximum. Total ADC conversion time is the product of 25 ms and enabled channel counts. 0b: One-shot update. Do one set of conversion updates to registers REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C() after ADC_START = 1. 1b: Continuous update. Do a set of conversion updates to registers REG0x29/28(), REG0x27/26(), REG0x2B/2A(), and REG0x2D/2C()every 1 sec. 6 ADC_START R/W 0b 0b: No ADC conversion 1b: Start ADC conversion. After the one-shot update is complete, this bit automatically resets to zero 5 ADC_FULLSCALE R/W 1b ADC input voltage range adjustment for PSYS and CMPIN ADC Channels. 2.04-V full scale holds 8 mV/LSB resolution and 3.06-V full scale holds 12 mV/LSB resolution 0b: 2.04 V 1b: 3.06 V <default at POR>(Not accurate for REGN<6-V application (VBUS & VSYS< 6V)) 4-0 Reserved R/W 00000b Reserved Table 8-39. ADCOption Register (I2C address = 3Ah) Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 7 EN_ADC_CMPIN R/W 0b 0b: Disable <default at POR> 1b: Enable 6 EN_ADC_VBUS R/W 0b 0b: Disable <default at POR> 1b: Enable 5 EN_ADC_PSYS R/W 0b 0b: Disable <default at POR> 1b: Enable 4 EN_ADC_IIN R/W 0b 0b: Disable <default at POR> 1b: Enable 3 EN_ADC_IDCHG R/W 0b 0b: Disable <default at POR> 1b: Enable www.ti.com BQ25730 SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: BQ25730 |
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