BQ25713 datasheet(40/111 Pages) TI2

40 / 111 page

SCL

SDA

A = Start condition

G = MSB of data clocked into host

B = MSB of address clocked into target

H = LSB of data clocked into host

C = LSB of address clocked into target

I = Acknowledge clock pulse

D = R/W bit clocked into target

J = Stop condition

E = Target pulls SDA line low

K = New start condition

F = ACKNOWLEDGE bit clocked into host

Figure 8-7. I2C Read Timing

8.5.1.2 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the

data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each

data bit transferred.

SDA

SCL

Data line stable;

Data valid

Change

of data

allowed

Figure 8-8. Bit Transfer on the I2C Bus

8.5.1.3 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the host. The bus is considered busy after the START

condition, and free after the STOP condition.

BQ25730

SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024

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BQ25713 Datasheet(PDF) 40 Page - Texas Instruments