BQ25713 datasheet(29/111 Pages) TI2

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Table 8-1. Maximum Input Current Limit Configuration Table

INDUCTANCE (IADPT Pin

Resistance)

EN_FAST_5MOHM

RSR_RAC BIT

MAXIMUM INPUT CURRENT LIMIT

(IINDPM)

1.0 uH(90.9 kΩ)

1.5 uH(121 kΩ)

2.2 uH(137 kΩ)

RSNS_RAC=0b

6.35 A

RSNS_RAC=1b

6.35 A

RSNS_RAC=1b

10 A

3.3 uH(169 kΩ)

RSNS_RAC=0b

6.35 A

RSNS_RAC=1b

10 A

8.3.6 Input Voltage and Current Limit Setup

The actual input current limit being adopted by the device is the lower setting of IIN_DPM and ILIM_HIZ pin.

• When adapter is removed (CHRG_OK is not valid). Note when adapter is removed IIN_HOST will be reset

one time to 3.25 A, under battery only host is still able to overwrite IIN_HOST register with a new value. If the

adapter plug back in and CHRG_OK is pulled up, IIN_HOST will not be reset again.

• When input current optimization (ICO) is executed (EN_ICO_MODE=1b), the charger will automatically detect

the optimized input current limit based on adapter output characteristic. The final IIN_DPM register setting

could be different from IIN_HOST after ICO.

The voltage regulation loop of the charger regulates the input voltage to prevent the input adapter collapsing.

The VINDPM threshold should be configured based on no load input voltage level.Charger initiates a VBUS

voltage measurement without any load (VBUS at no load) right before the converter is enabled. The default

VINDPM threshold is VBUS at no load – 1.28 V. Host can adjust VINDPM threshold after device POR through

InputVoltage register(0x0B/0Ah[]), range from 3.2V to 19.52V with LSB 64mV.

After input current and voltage limits are set, the charger device is ready to power up. The host can always

program the input current and voltage limit after the charger being powered up based on the input source type.

8.3.7 Battery Cell Configuration

CELL_BATPRESZ pin is biased with a resistor divider from VDDA to GND. After REGN LDO is activated

(VDDA rise up), the device detects the battery configuration through CELL_BATPRESZ pin bias voltage. No

external cap is allowed at CELL_BATPRESZ pin. When CELL_BATPRESZ pin is pulled down to GND (because

of battery removal) at the beginning of startup process, VSYS_MIN = 3.6 V and SYS_OVP = 25 V and

Maximum charge voltage (REG0x05/04)) follow 1 cell default setting 4.2 V. VSYS and VBAT ADC offset is

also determined by CELL_BATPRESZ pin setting, under 1S-4S VSYS/VBAT ADC holds 2.88-V offset, however

under 5S detection VSYS/VBAT ADC only holds 8.16-V offset to cover higher voltage range. Refer to Table 8-2

for CELL_BATPRESZ pin configuration typical voltage for swept cell count.

Table 8-2. Battery Cell Configuration

CELL COUNT

PIN VOLTAGE w.r.t.

VDDA

CHARGEVOLTAGE

(REG0x05/04h)

SYSOVP

VSYS_MIN

VSYS/VBAT

ADC OFFSET

100%(Directly connect to

VDDA)

21.000 V

25 V

15.4 V

8.16 V

75%

16.800 V

19.5 V

12.3 V

2.88 V

55%

12.600 V

19.5 V

9.2 V

2.88 V

40%

8.400 V

12 V

6.6 V

2.88 V

25%

4.200 V

6 V

3.6 V

2.88 V

Battery removal

4.200 V

25 V

3.6 V

2.88 V

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BQ25730

SLUSE65A – FEBRUARY 2021 – REVISED JANUARY 2024

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